1. Field of the Invention
This invention relates to a device, especially, a DLL (Delay Locked Loop) circuit unit for use in a semiconductor memory such as a DRAM chip comprising a DLL circuit mounted thereon.
2. Description of Related Art
A DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) employs a DLL circuit, which generates internal clock signals in synchronization with external clock signals, for minimizing the delay in operation within the memory.
After being turned ON, DLL circuits require a predetermined period before being able to output stable internal clock signals, and this period is hereafter referred to as the “start-up period”.
In other words, DLL circuits require the start-up period to transit from the non-operating state to the operating state.
Japanese Laid-Open Patent Publication No. 2007-115366 (Patent Document 1), for example, describes a semiconductor device comprising a counter circuit which counts the period required for a DLL circuit to stabilize its operation, for example, tXPDLL (the period required to enable input of a read or synchronous mode ODT (On Die Termination) from exit from the slow precharge power-down mode), and masks the DLL circuit during this period.